hardcaml-yosys

Import Verilog designs into HardCaml
IN THIS PACKAGE
Module HardCamlYosys . Techlib . Simlib . Mem . P
type !'a t = {
abits : 'a;
init : 'a;
memid : 'a;
offset : 'a;
size : 'a;
width : 'a;
rd_clk_enable : 'a;
rd_clk_polarity : 'a;
rd_ports : 'a;
rd_transparent : 'a;
wr_clk_enable : 'a;
wr_clk_polarity : 'a;
wr_ports : 'a;
}
val t : (string * int) t
val map : ( 'a -> 'b ) -> 'a t -> 'b t
val map2 : ( 'a -> 'b -> 'c ) -> 'a t -> 'b t -> 'c t
val to_list : 'a t -> 'a list