hardcaml-yosys

Import Verilog designs into HardCaml
IN THIS PACKAGE
type dyn = Yojson.Safe.json
type direction = Yosys_atd_t.direction
type bits = Yosys_atd_t.bits
type port = Yosys_atd_t.port = {
direction : direction;
bits : bits;
}
type param_value = Yosys_atd_t.param_value
type attributes = Yosys_atd_t.attributes = {
src : string;
full_case : int;
parallel_case : int;
init : dyn option;
unused_bits : string option;
}
type netname = Yosys_atd_t.netname = {
hide_name : int;
bits : bits;
attributes : attributes;
}
type cell = Yosys_atd_t.cell = {
hide_name : int;
typ : string;
parameters : (string * param_value) list;
attributes : attributes;
port_directions : (string * direction) list;
connections : (string * bits) list;
}
type modl = Yosys_atd_t.modl = {
ports : (string * port) list;
cells : (string * cell) list;
netnames : (string * netname) list;
}
type t = Yosys_atd_t.t = {
creator : string;
modl : (string * modl) list;
}
val write_dyn : Bi_outbuf.t -> dyn -> unit
val string_of_dyn : ?len:int -> dyn -> string
val dyn_of_string : string -> dyn
val write_direction : Bi_outbuf.t -> direction -> unit
val string_of_direction : ?len:int -> direction -> string
val direction_of_string : string -> direction
val write_bits : Bi_outbuf.t -> bits -> unit
val string_of_bits : ?len:int -> bits -> string
val bits_of_string : string -> bits
val write_port : Bi_outbuf.t -> port -> unit
val string_of_port : ?len:int -> port -> string
val port_of_string : string -> port
val write_param_value : Bi_outbuf.t -> param_value -> unit
val string_of_param_value : ?len:int -> param_value -> string
val param_value_of_string : string -> param_value
val write_attributes : Bi_outbuf.t -> attributes -> unit
val string_of_attributes : ?len:int -> attributes -> string
val attributes_of_string : string -> attributes
val write_netname : Bi_outbuf.t -> netname -> unit
val string_of_netname : ?len:int -> netname -> string
val netname_of_string : string -> netname
val write_cell : Bi_outbuf.t -> cell -> unit
val string_of_cell : ?len:int -> cell -> string
val cell_of_string : string -> cell
val write_modl : Bi_outbuf.t -> modl -> unit
val string_of_modl : ?len:int -> modl -> string
val modl_of_string : string -> modl
val write_t : Bi_outbuf.t -> t -> unit
val string_of_t : ?len:int -> t -> string
val t_of_string : string -> t