package hardcaml_axi

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package hardcaml_axi
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Register bank attached directly to the AXI bus. Under the hood, this uses Internal_bus.Register_bank

val sexp_of_t : ('a -> Sexplib0.Sexp.t) -> 'a t -> Sexplib0.Sexp.t
val create : Hardcaml.Scope.t -> reg_spec:Hardcaml.Reg_spec.t -> axi_master:Hardcaml.Signal.t Master_to_slave.t -> write_modes:Register_mode.t Base.list -> read_values:Hardcaml.Signal.t Base.list -> Hardcaml.Signal.t t
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