package hardcaml_xilinx_reports

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Primitive group definitions for Xilinx Vivado Ultrascale designs. See ug974.

Groups and subgroups define properties of cells within the Vivado database. They are used to access properties of a cells and nets. In particular, here we are interested in properties related to utilization.

They are used by selecting all cells in a module, then filtering those with the appropriate property. The number of such cells left is the corresponding total utilization count.

The most important groups are Clb, Register and Blockram.

module type Subgroup = sig ... end
module Advanced : sig ... end
module Arithmetic : sig ... end
module Blockram : sig ... end
module Clb : sig ... end
module Clock : sig ... end
module Configuration : sig ... end
module Io : sig ... end
module Register : sig ... end
type t

Primitive groups

*

val sexp_of_t : t -> Sexplib0.Sexp.t
val advanced : Advanced.t Hardcaml_xilinx_reports__.Import.List.t -> t
val arithmetic : Arithmetic.t Hardcaml_xilinx_reports__.Import.List.t -> t
val blockram : Blockram.t Hardcaml_xilinx_reports__.Import.List.t -> t
val clb : Clb.t Hardcaml_xilinx_reports__.Import.List.t -> t
val clock : Clock.t Hardcaml_xilinx_reports__.Import.List.t -> t
val configuration : Configuration.t Hardcaml_xilinx_reports__.Import.List.t -> t
val io : Io.t Hardcaml_xilinx_reports__.Import.List.t -> t
val register : Register.t Hardcaml_xilinx_reports__.Import.List.t -> t
val is_advanced : t -> Hardcaml_xilinx_reports__.Import.Bool.t
val is_arithmetic : t -> Hardcaml_xilinx_reports__.Import.Bool.t
val is_blockram : t -> Hardcaml_xilinx_reports__.Import.Bool.t
val is_clb : t -> Hardcaml_xilinx_reports__.Import.Bool.t
val is_clock : t -> Hardcaml_xilinx_reports__.Import.Bool.t
val is_configuration : t -> Hardcaml_xilinx_reports__.Import.Bool.t
val is_io : t -> Hardcaml_xilinx_reports__.Import.Bool.t
val is_register : t -> Hardcaml_xilinx_reports__.Import.Bool.t
val advanced_val : t -> Advanced.t Hardcaml_xilinx_reports__.Import.List.t Hardcaml_xilinx_reports__.Import.Option.t
val arithmetic_val : t -> Arithmetic.t Hardcaml_xilinx_reports__.Import.List.t Hardcaml_xilinx_reports__.Import.Option.t
val blockram_val : t -> Blockram.t Hardcaml_xilinx_reports__.Import.List.t Hardcaml_xilinx_reports__.Import.Option.t
val clb_val : t -> Clb.t Hardcaml_xilinx_reports__.Import.List.t Hardcaml_xilinx_reports__.Import.Option.t
val clock_val : t -> Clock.t Hardcaml_xilinx_reports__.Import.List.t Hardcaml_xilinx_reports__.Import.Option.t
val configuration_val : t -> Configuration.t Hardcaml_xilinx_reports__.Import.List.t Hardcaml_xilinx_reports__.Import.Option.t
val io_val : t -> Io.t Hardcaml_xilinx_reports__.Import.List.t Hardcaml_xilinx_reports__.Import.Option.t
val register_val : t -> Register.t Hardcaml_xilinx_reports__.Import.List.t Hardcaml_xilinx_reports__.Import.Option.t
module Variants : sig ... end
val primitive_group : t -> Hardcaml_xilinx_reports__.Import.String.t
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