Vivado synthesis project generation.
module Config : sig ... endProject configuration.
val create :
?database:Hardcaml.Circuit_database.t ->
?config:Config.t ->
?place:Hardcaml_xilinx_reports__.Import.Bool.t ->
?route:Hardcaml_xilinx_reports__.Import.Bool.t ->
?checkpoint:Hardcaml_xilinx_reports__.Import.Bool.t ->
clocks:Clock.t Hardcaml_xilinx_reports__.Import.List.t ->
part_name:Hardcaml_xilinx_reports__.Import.String.t ->
output_path:Hardcaml_xilinx_reports__.Import.String.t ->
Hardcaml.Circuit.t ->
tCreate a Vivado project. This consists of the RTL generated for the given Circuit.t and project files. The function should be passed a list of top level clocks which specify the port name and requested frequency. part_name is the full FPGA part name including package a speed-grade. Files will be written to output_path. Performs synthesis by default but will also optionally run placement and routing.
val run :
?verbose:Hardcaml_xilinx_reports__.Import.Bool.t ->
?path_to_vivado:Hardcaml_xilinx_reports__.Import.String.t ->
t ->
Report.t Hardcaml_xilinx_reports__.Import.Option.t Async.Deferred.tExecute a project generated with create.
Uses Unix.system to run vivado in batch mode.
val output_path : t -> Hardcaml_xilinx_reports__.Import.String.tOutput path where reports, artifacts and verilog files for this project lives.