package hardcaml_xilinx_reports

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Reading of report files generated by the synthesis project.

module Subgroup : sig ... end
module Group : sig ... end
module Clock : sig ... end
type t = {
  1. groups : Group.t Hardcaml_xilinx_reports__.Import.List.t;
  2. clocks : Clock.t Hardcaml_xilinx_reports__.Import.List.t;
}

Utilization and timing report data.

val sexp_of_t : t -> Sexplib0.Sexp.t
val read : file_name:Hardcaml_xilinx_reports__.Import.String.t -> t

Read back a report file generated by the vivado project tcl script and convert to a tree of groups and subgroups. Includes the total module setup and hold slack.

val print_utilization_table : file:Hardcaml_xilinx_reports__.Import.Out_channel.t -> top_level_name:Hardcaml_xilinx_reports__.Import.String.t -> circuits:Hardcaml.Circuit.t Hardcaml_xilinx_reports__.Import.List.t -> (Hardcaml_xilinx_reports__.Import.String.t * t Hardcaml_xilinx_reports__.Import.Option.t) Hardcaml_xilinx_reports__.Import.List.t -> Hardcaml_xilinx_reports__.Import.Unit.t

Prints the utilization table hierarchically.

val print_timing_table : file:Hardcaml_xilinx_reports__.Import.Out_channel.t -> top_level_name:Hardcaml_xilinx_reports__.Import.String.t -> circuits:Hardcaml.Circuit.t Hardcaml_xilinx_reports__.Import.List.t -> (Hardcaml_xilinx_reports__.Import.String.t * t Hardcaml_xilinx_reports__.Import.Option.t) Hardcaml_xilinx_reports__.Import.List.t -> Hardcaml_xilinx_reports__.Import.Unit.t

Prints the timing table hierarchically.

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