package hardcaml_xilinx_reports

  1. Overview
  2. Docs

Run Vivado and create a synthesis timing and utilization report for a design.

module Clock : sig ... end

Define properties of clocks on the top level module. The most important properties are the clock net name and it's period.

module Command : sig ... end

Generate a generic command line for performing synthesis runs over a given design.

module Primitive_group : sig ... end

Primitive group definitions for Xilinx Vivado Ultrascale designs. See ug974.

module Project : sig ... end

Vivado synthesis project generation.

module Report : sig ... end

Reading of report files generated by the synthesis project.

module Wrap_with_registers : sig ... end
OCaml

Innovation. Community. Security.