hardcaml

Register Transfer Level hardware design in OCaml
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Class type
Library HardCaml
Module HardCaml . Signal . Comb
type t = Types.signal
val empty : t
val (--) : t -> string -> t
val width : t -> int
val constb : string -> t
val consti : int -> int -> t
val consti32 : int -> int32 -> t
val consti64 : int -> int64 -> t
val consthu : int -> string -> t
val consths : int -> string -> t
val constd : int -> string -> t
val constv : string -> t
val constibl : int list -> t
val const : string -> t
val concat : t list -> t
val concat_e : t list -> t
val (@:) : t -> t -> t
val vdd : t
val gnd : t
val zero : int -> t
val ones : int -> t
val one : int -> t
val select : t -> int -> int -> t
val select_e : t -> int -> int -> t
val bit : t -> int -> t
val msb : t -> t
val lsbs : t -> t
val lsb : t -> t
val msbs : t -> t
val drop_bottom : t -> int -> t
val drop_top : t -> int -> t
val sel_bottom : t -> int -> t
val sel_top : t -> int -> t
val insert : t:t -> f:t -> int -> t
val sel : t -> (int * int) -> t
val mux : t -> t list -> t
val mux2 : t -> t -> t -> t
val mux_init : t -> int -> ( int -> t ) -> t
val cases : t -> t -> (int * t) list -> t
val matches : ?resize:( t -> int -> t ) -> ?default:t -> t -> (int * t) list -> t
val pmux : (t * t) list -> t -> t
val pmuxl : (t * t) list -> t
val pmux1h : (t * t) list -> t
val (&:) : t -> t -> t
val (&:.) : t -> int -> t
val (&&:) : t -> t -> t
val (|:) : t -> t -> t
val (|:.) : t -> int -> t
val (||:) : t -> t -> t
val (^:) : t -> t -> t
val (^:.) : t -> int -> t
val (~:) : t -> t
val (+:) : t -> t -> t
val (+:.) : t -> int -> t
val (-:) : t -> t -> t
val (-:.) : t -> int -> t
val negate : t -> t
val (*:) : t -> t -> t
val (*+) : t -> t -> t
val (==:) : t -> t -> t
val (==:.) : t -> int -> t
val (<>:) : t -> t -> t
val (<>:.) : t -> int -> t
val (<:) : t -> t -> t
val (<:.) : t -> int -> t
val lt : t -> t -> t
val (>:) : t -> t -> t
val (>:.) : t -> int -> t
val (<=:) : t -> t -> t
val (<=:.) : t -> int -> t
val (>=:) : t -> t -> t
val (>=:.) : t -> int -> t
val (<+) : t -> t -> t
val (<+.) : t -> int -> t
val (>+) : t -> t -> t
val (>+.) : t -> int -> t
val (<=+) : t -> t -> t
val (<=+.) : t -> int -> t
val (>=+) : t -> t -> t
val (>=+.) : t -> int -> t
val to_string : t -> string
val to_int : t -> int
val to_sint : t -> int
val to_int32 : t -> int32
val to_sint32 : t -> int32
val to_int64 : t -> int64
val to_sint64 : t -> int64
val to_bstr : t -> string
val bits : t -> t list
val to_array : t -> t array
val of_array : t array -> t
val wire : int -> t
val wireof : t -> t
val (<==) : t -> t -> unit
val assign : t -> t -> unit
val input : string -> int -> t
val output : string -> t -> t
val clock : t
val reset : t
val clear : t
val enable : t
val repeat : t -> int -> t
val split : t -> t * t
val sll : t -> int -> t
val srl : t -> int -> t
val sra : t -> int -> t
val log_shift : ( t -> int -> t ) -> t -> t -> t
val uresize : t -> int -> t
val sresize : t -> int -> t
val ue : t -> t
val se : t -> t
val resize_list : resize:( t -> int -> t ) -> t list -> t list
val resize_op2 : resize:( t -> int -> t ) -> ( t -> t -> t ) -> t -> t -> t
val reduce : ( 'a -> 'a -> 'a ) -> 'a list -> 'a
val reverse : t -> t
val mod_counter : int -> t -> t
val tree : int -> ( 'a list -> 'a ) -> 'a list -> 'a
val binary_to_onehot : t -> t
val onehot_to_binary : t -> t
val binary_to_gray : t -> t
val gray_to_binary : t -> t
val srand : int -> t
module type TypedMath = sig ... end
module Signed : TypedMath
module Uop : sig ... end
module Sop : sig ... end