hardcaml

Register Transfer Level hardware design in OCaml
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Library HardCaml
Module HardCaml . Signal . Types
type signal_op =
| Signal_add
| Signal_sub
| Signal_mulu
| Signal_muls
| Signal_and
| Signal_or
| Signal_xor
| Signal_eq
| Signal_not
| Signal_lt
| Signal_cat
| Signal_mux
type uid = int64
module UidMap : sig ... end
module UidSet : sig ... end
type signal_id = {
s_id : uid;
mutable s_names : string list;
s_width : int;
mutable s_deps : signal list;
}
and signal =
| Signal_empty
| Signal_const of signal_id * string
| Signal_op of signal_id * signal_op
| Signal_wire of signal_id * signal ref
| Signal_select of signal_id * int * int
| Signal_reg of signal_id * register
| Signal_mem of signal_id * uid * register * memory
| Signal_inst of signal_id * uid * instantiation
and register = {
reg_clock : signal;
reg_clock_level : signal;
reg_reset : signal;
reg_reset_level : signal;
reg_reset_value : signal;
reg_clear : signal;
reg_clear_level : signal;
reg_clear_value : signal;
reg_enable : signal;
}
and memory = {
mem_size : int;
mem_read_address : signal;
mem_write_address : signal;
}
and instantiation = {
inst_name : string;
inst_generics : (string * parameter) list;
inst_inputs : (string * signal) list;
inst_outputs : (string * (int * int)) list;
inst_lib : string;
inst_arch : string;
}
and parameter =
| ParamString of string
| ParamInt of int
| ParamFloat of float
| ParamBool of bool
val uid : signal -> uid
val depo : signal -> < data : signal list ; op1 : signal ; op2 : signal * signal ; sel : signal >
val deps : signal -> signal list
val names : signal -> string list
val width : signal -> int
val is_reg : signal -> bool
val is_mem : signal -> bool
val is_inst : signal -> bool
val is_const : signal -> bool
val is_select : signal -> bool
val is_wire : signal -> bool
val is_op : signal_op -> signal -> bool
val const_value : signal -> string
val new_id : unit -> uid
val reset_id : unit -> unit
val make_id : int -> signal list -> signal_id
val string_of_op : signal_op -> string
val to_string : signal -> string
val structural_compare : ?check_names:bool -> ?check_deps:bool -> signal -> signal -> bool