package hardcaml-llvmsim

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in-package search v0.2.0

hardcaml-llvmsim
- HardCamlLlvmsim
  - Compile
  - Globals
  - Info
  - Sim
    
    Gen
    
    Make
  - Utils

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Module
Module type
Parameter
Class
Class type

type global_type =

| G_Port
| G_Internal
| G_Reg
| G_Mem

type global = {

width : int;
rnd_width : int;
cur : Llvm.llvalue;
next : Llvm.llvalue;
typ : global_type;

}

type global_simple = bool -> int -> HardCaml.Signal.Types.signal -> global

type global_reg = int -> HardCaml.Signal.Types.signal -> global

type global_mem = int -> int -> HardCaml.Signal.Types.signal -> global

type load_simple = bool -> HardCaml.Signal.Types.signal -> Llvm.llvalue

type load_reg = HardCaml.Signal.Types.signal -> Llvm.llvalue

type load_mem = Llvm.llvalue -> HardCaml.Signal.Types.signal -> Llvm.llvalue

type store_simple =
  Llvm.llvalue ->
  bool ->
  HardCaml.Signal.Types.signal ->
  unit

type store_reg = Llvm.llvalue -> HardCaml.Signal.Types.signal -> unit

type store_mem = Llvm.llvalue -> HardCaml.Signal.Types.signal -> unit

type update_reg = HardCaml.Signal.Types.signal -> unit

type update_mem = Llvm.llvalue -> HardCaml.Signal.Types.signal -> unit

type globals = {

gmap : global HardCaml.Signal.Types.UidMap.t Stdlib.ref;
gsimple : global_simple;
greg : global_reg;
gmem : global_mem;
fscope : Llvm.llvalue Utils.func -> func;

}

and func = {

loads : loads;
stores : stores;
updates : updates;

}

and loads = {

lsimple : load_simple;
lreg : load_reg;
lmem : load_mem;

}

and stores = {

ssimple : store_simple;
sreg : store_reg;
smem : store_mem;

}

and updates = {

ureg : update_reg;
umem : update_mem;

}

val global_fns : Llvm.llmodule -> globals

val load_signal : 
  ?rd_mem:bool ->
  func ->
  Llvm.llvalue HardCaml.Signal.Types.UidMap.t ->
  HardCaml.Signal.Types.signal ->
  Llvm.llvalue HardCaml.Signal.Types.UidMap.t * Llvm.llvalue

val store_signal : func -> Llvm.llvalue -> HardCaml.Signal.Types.signal -> unit