package hardcaml

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type !'a cyclesim = {
  1. sim_in_ports : (string * 'a Pervasives.ref) list;
  2. sim_out_ports : (string * 'a Pervasives.ref) list;
  3. sim_internal_ports : (string * 'a Pervasives.ref) list;
  4. sim_reset : unit -> unit;
  5. sim_cycle_comb : unit -> unit;
  6. sim_cycle : unit -> unit;
}
val cycle : 'a cyclesim -> unit
val cycle_comb : 'a cyclesim -> unit
val reset : 'a cyclesim -> unit
val in_port : 'a cyclesim -> string -> 'a Pervasives.ref
val out_port : 'a cyclesim -> string -> 'a Pervasives.ref
val internal_port : 'a cyclesim -> string -> 'a Pervasives.ref
val in_ports : 'a cyclesim -> (string * 'a Pervasives.ref) list
val out_ports : 'a cyclesim -> (string * 'a Pervasives.ref) list
val internal_ports : 'a cyclesim -> (string * 'a Pervasives.ref) list
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