package hardcaml

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package hardcaml
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module Of_signal : sig ... end
type tag
val iter : Of_signal.t -> f:(Signal.t -> Base.unit) -> Base.unit
val map : Of_signal.t -> f:(Signal.t -> Signal.t) -> Of_signal.t
val to_list : Of_signal.t -> Signal.t Base.list
val to_alist : Of_signal.t -> (tag * Signal.t) Base.list
val of_alist : (tag * Signal.t) Base.list -> Of_signal.t
module Unsafe_assoc_by_port_name : sig ... end
val fold : Of_signal.t -> init:'acc -> f:('acc -> Signal.t -> 'acc) -> 'acc
val fold2 : Of_signal.t -> Of_signal.t -> init:'acc -> f:('acc -> Signal.t -> Signal.t -> 'acc) -> 'acc
module Names_and_widths : sig ... end