package hardcaml

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Module
Module type
Parameter
Class
Class type
module Language : sig ... end
module Output_mode : sig ... end

RTL generation options.

val output : ?output_mode:Output_mode.t -> ?database:Circuit_database.t -> Language.t -> Circuit.t -> Base.Unit.t

Write circuit to Verilog or Vhdl. Instantiations are (recursively) looked up in database and if a circuit exists it is also written. The output_mode specifies how the circuit should be written - either to a single file (or buffer, or channel) or to a directory with one file for each for the top level circuit and any instantiated circuits contained in the database.

val print : ?database:Circuit_database.t -> Language.t -> Circuit.t -> Base.Unit.t

print is output ~output_mode:(To_channel stdout)

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