package hardcaml

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Icarus Verilog Cosimulation interface

type delta_message = {
  1. sets : (Base.String.t * Base.String.t) Base.List.t;
  2. gets : Base.String.t Base.List.t;
  3. delta_time : Base.Int64.t;
}

run sets, then gets then schedule next callback at cur_time+delta_time

type init_message = Base.String.t Base.List.t

expected inputs and outputs

type control_message =
  1. | Finish
  2. | Run of delta_message

control message

type response_message = (Base.String.t * Base.String.t) Base.List.t

response message

val net_addr : Base.String.t
val net_port : Base.Int.t
module Comms : sig ... end

basic TCP communications between client (simulation) and server (hardcaml)

send a control message to the simulation

val write_testbench : ?dump_file:Base.String.t -> name:Base.String.t -> inputs:(Base.String.t * Base.Int.t) Base.List.t -> outputs:(Base.String.t * Base.Int.t) Base.List.t -> (Base.String.t -> Base.Unit.t) -> Base.Unit.t

write test harness

val write_testbench_from_circuit : ?dump_file:Base.String.t -> (Base.String.t -> Base.Unit.t) -> Circuit.t -> Base.Unit.t

write test hardness derivied from a hardcaml circuit

compile verilog files to a vvp simulation object

val derive_clocks_and_resets : Circuit.t -> Base.String.t Base.List.t * Base.String.t Base.List.t

find clocks and resets in a hardcaml circuit

val load_sim : Base.String.t -> Base.Unit.t

load vvp file into simulator along with vpi object

val compile_and_load_sim : ?dump_file:Base.String.t -> Circuit.t -> Base.Unit.t

compile circuit and load simulation

val make : ?dump_file:Base.String.t -> Circuit.t -> Cyclesim.t_port_list

create simulator from hardcaml circuit

module With_interface (I : Interface.S) (O : Interface.S) : sig ... end
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