package hardcaml_axi

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Instantiates an AXI Stream interface S from the given config.

Parameters

module X : Config

Signature

module Source : sig ... end

AXI4-stream data source ports

module Dest : sig ... end

AXI4-stream data acknowledgement ports

val add_properties : ?clear:Hardcaml.Signal.t -> ?prefix:Base.string -> source:Hardcaml.Signal.t Source.t -> dest:Hardcaml.Signal.t Dest.t -> Hardcaml.Scope.t -> Base.unit
module Datapath_register : sig ... end

When placed between two components which produce/consume an AXI stream, this module ensures that every output signal is registerd. It fully supports the tvalid/tready handshake protocol.

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