package hardcaml_axi

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Write configuration of a register from the core interface.

module Mode : sig ... end
type t
val sexp_of_t : t -> Sexplib0.Sexp.t

Creation of write modes

*

val create : ?internal_clear:bool -> ?clear_to:int -> Mode.t -> t

Create a configuration for a write register. internal_clear allows the register to be cleared by user logic. clear_to is the initial value of the register after claer.

val hold : t

Register holds it's value after a write.

val hold_with_internal_clear : t

Like hold expect the register may be cleared by user logic.

val toggle_high : t

Register takes the written value for 1 cycle, then sets itself high.

val toggle_low : t

Register takes the written value for 1 cycle, then sets itself low.

Fields

val internal_clear : t -> bool
val clear_to : t -> int
val mode : t -> Mode.t
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