package hardcaml_circuits

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package hardcaml_circuits
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Convert an arbitrary input vector to onehot. The first bit set scanning from either the lsb or msb will be set in the output and all others will be 0. The architecture has logarithmic delay.

examples (with scan_from_msb):

  • 1111 -> 1000
  • 0000 -> 0000
  • 0110 -> 0100
type 'a t = {
  1. any_bit_set : 'a;
  2. data : 'a;
}
val scan_from_msb : (module Hardcaml.Comb.S with type t = 'a) -> 'a -> 'a t
val scan_from_lsb : (module Hardcaml.Comb.S with type t = 'a) -> 'a -> 'a t
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