package hardcaml_step_testbench

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package hardcaml_step_testbench
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module Monads : sig ... end
module type S = sig ... end
include S
include Imperative.S with module Step_monad = Monads.Step_monad
module No_data : Digital_components.Data.S with type t = unit
module Step_monad = Monads.Step_monad
type 'a t = ('a, No_data.t, No_data.t) Step_monad.t
include Core.Monad.S with type 'a t := 'a t
val (>>=) : 'a t -> ('a -> 'b t) -> 'b t
val (>>|) : 'a t -> ('a -> 'b) -> 'b t
module Monad_infix : sig ... end
val bind : 'a t -> f:('a -> 'b t) -> 'b t
val return : 'a -> 'a t
val map : 'a t -> f:('a -> 'b) -> 'b t
val join : 'a t t -> 'a t
val ignore_m : 'a t -> unit t
val all : 'a t list -> 'a list t
val all_unit : unit t list -> unit t
module Let_syntax : sig ... end
val cycle : ?num_cycles:int -> unit -> unit t

cycle i_data ~num_cycles waits for num_cycles cycles of the simulator to run. cycle raises if num_cycles < 1.

val for_ : int -> int -> (int -> unit t) -> unit t

for_ i j f does f i, f (i+1), ... f j in sequence. If j < i, then for_ i j immediately returns unit.

val start : ('a -> 'b t) -> 'a -> ('b, No_data.t) Step_monad.Component_finished.t t
type 'a finished_event = ('a, unit) Step_monad.Component_finished.t Step_monad.Event.t
val spawn : (unit -> 'a t) -> 'a finished_event t

Launch a new task within the current simulation step.

val wait_for : 'a finished_event -> 'a t

Wait for the given event to occur, and extract its return value.

val wait_for_with_timeout : 'a finished_event -> timeout_in_cycles:int -> 'a option t

Like wait_for except it stops waiting after timeout_in_cycles and returns None. Note that the spawned task continues to execute.

module List : sig ... end
module Array : sig ... end
val run_with_timeout : ?update_children_after_finish:bool -> ?timeout:int -> unit -> simulator:(_, _) Hardcaml.Cyclesim.t -> testbench:(No_data.t -> 'a t) -> 'a option

Run the testbench until the main task finishes.

The optional timeout argument stops the simulation after the given number of steps and returns None. Otherwise it will continue until the testbech completes.

val run_until_finished : ?update_children_after_finish:bool -> unit -> simulator:(_, _) Hardcaml.Cyclesim.t -> testbench:(No_data.t -> 'a t) -> 'a

Run the testbench until completion.

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