package hardcaml_waveterm

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hardcaml_waveterm
- Hardcaml_waveterm
  - Expert
    
    M
    
    Data
    
    S
    
    Expect
    
    Render
    
    Bounds
    
    Make
    
    G
    
    Static
    
    R
    
    Styles
    
    Serialize
    
    Wave
    
    Waveform
    
    Waves
    
    Config
    
    Make
    
    Data
    
    Expect
    
    Render
    
    Bounds
    
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    R
    
    Styles
    
    Serialize
    
    Wave
    
    Waveform
    
    Waves
    
    Config
  - For_cyclesim
    
    Expect
    
    Serialize
    
    Waveform
hardcaml_waveterm.cyclesim
- Hardcaml_waveterm_cyclesim
  - Expert
  - Render
    
    Bounds
    
    Make
    
    G
    
    Static
    
    R
    
    Styles
  - Wave
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hardcaml_waveterm.event_store
- Hardcaml_waveterm_event_store
  - Bits_store
    
    Data
    
    Event_store
    
    Time
  - Event_store
    
    Make
    
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  - Event_store_intf
    
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hardcaml_waveterm.interactive
- Hardcaml_waveterm_interactive
  - Draw_notty
  - Scroll
    
    Adjustment
    
    HScrollbar
    
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    Orientation
    
    Scroll_bar_mode
    
    Scroll_bar_style
    
    Scrollable
    
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    Waves
    
    Config
hardcaml_waveterm.kernel
- Hardcaml_waveterm_kernel
  - Display_rule
    
    States
  - Display_rules
    
    With_interface
    
    I
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
  - Expert
    
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    In_memory
    
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    Wave
    
    Waveform
    
    Waves
    
    Config
    
    Make
    
    Data
    
    Render
    
    Bounds
    
    Make
    
    G
    
    Static
    
    R
    
    Styles
    
    Wave
    
    Waveform
    
    Waves
    
    Config
    
    Render
    
    M
    
    Data
    
    S
    
    Bounds
    
    Make
    
    G
    
    Static
    
    R
    
    Styles
    
    Wave
    
    Waves
    
    Config
    
    Make
    
    Bounds
    
    Data
    
    Make
    
    G
    
    Static
    
    R
    
    Styles
    
    Wave
    
    Waves
    
    Config
    
    S
    
    Bounds
    
    Data
    
    Make
    
    G
    
    Static
    
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    Styles
    
    Wave
    
    Waves
    
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    Wave
    
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    S
    
    Make
    
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    S
    
    Data
    
    Waveform
    
    M
    
    Data
    
    Render
    
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    Make
    
    G
    
    Static
    
    R
    
    Styles
    
    S
    
    Wave
    
    Waves
    
    Config
    
    Make
    
    Data
    
    Render
    
    Bounds
    
    Make
    
    G
    
    Static
    
    R
    
    Styles
    
    Wave
    
    Waves
    
    Config
    
    S
    
    Data
    
    Render
    
    Bounds
    
    Make
    
    G
    
    Static
    
    R
    
    Styles
    
    Wave
    
    Waves
    
    Config
    
    Waves
    
    M
    
    Data
    
    S
    
    Config
    
    Wave
    
    Make
    
    Config
    
    Data
    
    Wave
    
    S
    
    Config
    
    Data
    
    Wave
    
    Write
  - Port
    
    Type
  - Port_name
  - Text_alignment

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A Display_rules.t is an ordered list of rules that specifies the order of ports and the formatting of signals in a waveform.

A port is displayed according to the first rule that it matches, using that rule's wave format. Ports matching rules earlier in the list are displayed above ports matching rules later in the list.

type t = Display_rule.t Base.list

val sexp_of_t : t -> Sexplib0.Sexp.t

val run_rule : 
  Display_rule.t ->
  Port.t ->
  (Hardcaml.Wave_format.t Base.option * Text_alignment.t) Base.option

val sort_ports_and_formats : 
  t ->
  Port.t Base.list ->
  (Port.t * (Hardcaml.Wave_format.t Base.option * Text_alignment.t) Base.option)
    Base.list

Construct the port order and formatting from the display rules and ports (derived from a testbench simulation object). Unmatched ports are not shown, unless Rule.default (or a similar custom rule) is included as the last display rule.

val is_displayed : t -> Port.t -> Base.bool

Check if a given port is displayed by any of the rules.

val is_signal_displayed : t -> Hardcaml.Signal.t -> Base.bool

Check if a given signal (treated as an internal port) is displayed by any of the rules.

module With_interface (I : Hardcaml.Interface.S) : sig ... end

Create rules for each signal in the interface.