package hardcaml_xilinx_reports

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package hardcaml_xilinx_reports
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Vivado synthesis project generation.

module Config : sig ... end

Project configuration.

type t
val create : ?database:Hardcaml.Circuit_database.t -> ?config:Config.t -> ?place:Base.Bool.t -> ?route:Base.Bool.t -> ?checkpoint:Base.Bool.t -> clocks:Clock.t Base.List.t -> part_name:Base.String.t -> output_path:Base.String.t -> Hardcaml.Circuit.t -> t

Create a Vivado project. This consists of the RTL generated for the given Circuit.t and project files. The function should be passed a list of top level clocks which specify the port name and requested frequency. part_name is the full FPGA part name including package a speed-grade. Files will be written to output_path. Performs synthesis by default but will also optionally run placement and routing.

val run : ?verbose:Base.Bool.t -> ?path_to_vivado:Base.String.t -> t -> Report.t Base.Option.t Async.Deferred.t

Execute a project generated with create.

Uses Unix.system to run vivado in batch mode.

val output_path : t -> Base.String.t

Output path where reports, artifacts and verilog files for this project lives.

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