package hardcaml

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Module
Module type
Parameter
Class
Class type

Parameters

module S : Seq_spec

Signature

val reg_fb : ?clk:Types.signal -> ?clkl:Types.signal -> ?r:Types.signal -> ?rl:Types.signal -> ?rv:Types.signal -> ?c:Types.signal -> ?cl:Types.signal -> ?cv:Types.signal -> ?ge:Types.signal -> e:Types.signal -> w:int -> (Types.signal -> Types.signal) -> Types.signal
val pipeline : ?clk:Types.signal -> ?clkl:Types.signal -> ?r:Types.signal -> ?rl:Types.signal -> ?rv:Types.signal -> ?c:Types.signal -> ?cl:Types.signal -> ?cv:Types.signal -> ?ge:Types.signal -> n:int -> e:Types.signal -> Types.signal -> Types.signal
val g_reg : ?clk:Types.signal -> ?clkl:Types.signal -> ?r:Types.signal -> ?rl:Types.signal -> ?rv:Types.signal -> ?c:Types.signal -> ?cl:Types.signal -> ?cv:Types.signal -> ?ge:Types.signal -> e:Types.signal -> int -> Guarded.variable
val g_pipeline : ?clk:Types.signal -> ?clkl:Types.signal -> ?r:Types.signal -> ?rl:Types.signal -> ?rv:Types.signal -> ?c:Types.signal -> ?cl:Types.signal -> ?cv:Types.signal -> ?ge:Types.signal -> n:int -> e:Types.signal -> int -> Guarded.variable
val statemachine : ?clk:Types.signal -> ?clkl:Types.signal -> ?r:Types.signal -> ?rl:Types.signal -> ?rv:Types.signal -> ?c:Types.signal -> ?cl:Types.signal -> ?cv:Types.signal -> ?ge:Types.signal -> e:Types.signal -> 'a list -> ('a -> Types.signal) * ('a Guarded.cases -> Guarded.statement) * ('a -> Guarded.statement)
val memory : ?clk:Types.signal -> ?clkl:Types.signal -> ?r:Types.signal -> ?rl:Types.signal -> ?rv:Types.signal -> ?c:Types.signal -> ?cl:Types.signal -> ?cv:Types.signal -> ?ge:Types.signal -> int -> we:Types.signal -> wa:Types.signal -> d:Types.signal -> ra:Types.signal -> Types.signal
val ram_wbr : ?clk:Types.signal -> ?clkl:Types.signal -> ?r:Types.signal -> ?rl:Types.signal -> ?rv:Types.signal -> ?c:Types.signal -> ?cl:Types.signal -> ?cv:Types.signal -> ?ge:Types.signal -> int -> we:Types.signal -> wa:Types.signal -> d:Types.signal -> re:Types.signal -> ra:Types.signal -> Types.signal
val ram_rbw : ?clk:Types.signal -> ?clkl:Types.signal -> ?r:Types.signal -> ?rl:Types.signal -> ?rv:Types.signal -> ?c:Types.signal -> ?cl:Types.signal -> ?cv:Types.signal -> ?ge:Types.signal -> int -> we:Types.signal -> wa:Types.signal -> d:Types.signal -> re:Types.signal -> ra:Types.signal -> Types.signal
val multi_ram_wbr : ?priority_write:bool -> rd:Types.signal Multiram.read array -> wr:Types.signal Multiram.write array -> int -> Types.signal array
val multi_ram_rbw : ?priority_write:bool -> rd:Types.signal Multiram.read array -> wr:Types.signal Multiram.write array -> int -> Types.signal array
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