package hardcaml

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Module
Module type
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Class
Class type

Var declarations within the vcd. They make a name to a unique (short) identifier used in the VCD data section.

module Type : sig ... end

Various types of Vars.

type t
val sexp_of_t : t -> Sexplib0.Sexp.t
include Ppx_compare_lib.Comparable.S with type t := t
val compare : t -> t -> int
include Ppx_hash_lib.Hashable.S with type t := t
val hash_fold_t : Base.Hash.state -> t -> Base.Hash.state
val hash : t -> Base.Hash.hash_value
val create : ?typ:Type.t -> name:Base.string -> id:Base.string -> width:Base.int -> Base.unit -> t
val typ : t -> Type.t
val name : t -> Base.string
val id : t -> Base.string
val width : t -> Base.int
val define : Stdio.Out_channel.t -> t -> Base.unit
val write_string : Stdio.Out_channel.t -> t -> Base.string -> Base.unit
val write_bits : Stdio.Out_channel.t -> t -> Bits.t -> Base.unit
val write_four_state_vector : Stdio.Out_channel.t -> t -> Logic.Four_state_vector.t -> Base.unit
module Generator : sig ... end

Construct unique IDs for Vars.

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