package hardcaml_circuits

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package hardcaml_circuits
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val pipelined_tree_mux : cycles:int -> reg:(Hardcaml.Signal.t -> Hardcaml.Signal.t) -> selector:Hardcaml.Signal.t -> Hardcaml.Signal.t list -> Hardcaml.Signal.t
val pipelined_tree_priority_select : ?trace_reductions:bool -> ?pipelined_enable:Hardcaml.Signal.t -> cycles:int -> reg:(?enable:Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t) -> Hardcaml.Signal.t Hardcaml.With_valid.t list -> Hardcaml.Signal.t Hardcaml.With_valid.t
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