package hardcaml_circuits

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package hardcaml_circuits
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module Arbiters : sig ... end

Arbiter circuits. Given a set of requesters the arbiter chooses one to succeed.

module Cordic : sig ... end

Coordinate rotation digital computer.

module Cordic_reference : sig ... end

Reference implementation of the CORDIC algorithm using Float.t.

module Cordic_special_functions : sig ... end

CORDIC implementations of various different functions.

module Datapath_register : sig ... end

Register stage with up and downstream valid/ready control.

module Divider : sig ... end
module Counter_div_mod : sig ... end

A counter. If the current value is n, it outputs n/divisor (as quotient) and n mod divisor (as remainder). Since the counter doesn't track n directly, the maximum values must be specified as max_quotient and max_remainder, and the counter will wrap when its outputs reach max_quotient AND max_remainder.

module Fast_fifo : sig ... end

Low latency combinational fifo. See create for documentation.

module Fixnum : sig ... end
module Index_vec : sig ... end
module Lfsr : sig ... end

Linear feedback shift registers

module Modulo : sig ... end

Calculate x % y where x >= 0 and y > 0.

module Mul : sig ... end

Wallace/Dadda tree multipliers.

module Onehot_clean : sig ... end

Convert an arbitrary input vector to onehot. The first bit set scanning from either the lsb or msb will be set in the output and all others will be 0. The architecture has logarithmic delay.

module Pipelined_adder : sig ... end

Pipelined adder architectures for very wide adders.

module Pipelined_incrementer : sig ... end

Simple pipelined incrementer.

module Pipelined_tree_reduce : sig ... end

Pipelined tree reduce operation, with propogation delay equivalent to ceil(log(|args|))

module Pipelined_tree_mux : sig ... end
module Prefix_sum : sig ... end

Parallel prefix networks. See https://en.wikipedia.org/wiki/Prefix_sum.

module Rac : sig ... end

ROM-accumulator.

module Sorting_network : sig ... end

Sorting networks.

module Stack : sig ... end

Synchronous stack implementation

module Stages : sig ... end

Represents a computation broken into multiple stages. Each stage is returned in an array.

module Vec : sig ... end

A simple vector structure with insert and delete operations at arbitrary positions.

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