package hardcaml_xilinx

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package hardcaml_xilinx
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val create : ?read_latency:Base.int -> ?overflow_check:Base.bool -> ?showahead:Base.bool -> ?underflow_check:Base.bool -> ?build_mode:Hardcaml.Build_mode.t -> ?scope:Hardcaml.Scope.t -> ?fifo_memory_type:Fifo_memory_type.t -> ?instance:Base.string -> ?xpm_version:[ `Xpm_2019_1 | `Xpm_2022_1 ] -> ?cascade_height:Base.int -> ?nearly_full:Base.int -> ?nearly_empty:Base.int -> Base.unit -> capacity:Base.int -> clock:Hardcaml.Signal.t -> clear:Hardcaml.Signal.t -> wr:Hardcaml.Signal.t -> d:Hardcaml.Signal.t -> rd:Hardcaml.Signal.t -> Hardcaml.Signal.t Hardcaml.Fifo.t

Create a synchronous FIFO with the given capacity. If build_mode is Simulation a hardcaml model is generated (note, though, the model is synthesizable). Otherwise a XPM primitive FIFO is instantiated.

If the overflow_check (resp underflow_check)) logic is enabled a write will not occur when the fifo is full (resp read when empty).

showahead reduces the fifo read latency from 1 to 0 cycles relative to rd. Optionally the read_latency can be increased when showahead is false, to add extra pipelining to the FIFO output.

module With_interface (X : Hardcaml.Interface.S) : sig ... end
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