package hardcaml_xilinx_reports

You can search for identifiers within the package.

in-package search v0.2.0

hardcaml_xilinx_reports
- Hardcaml_xilinx_reports
  - Clock
  - Command
    
    Command_flags
    
    With_interface
    
    I
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
  - Primitive_group
    
    Advanced
    
    Variants
    
    Arithmetic
    
    Variants
    
    Blockram
    
    Variants
    
    Clb
    
    Variants
    
    Clock
    
    Variants
    
    Configuration
    
    Variants
    
    Io
    
    Variants
    
    Register
    
    Variants
    
    Subgroup
    
    Variants
  - Project
    
    Config
  - Report
    
    Clock
    
    Group
    
    Subgroup
  - Wrap_with_registers
    
    Make
    
    I
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    I_with_clock
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    Make_sequential
    
    I
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name

Legend:
Library
Module
Module type
Parameter
Class
Class type

Define properties of clocks on the top level module. The most important properties are the clock net name and it's period.

We also allow specification of the input BUFG driving the clock pin. This is optional, but allows the synthesizer to approximate skew across the device. It is specified at a bufg location constraint ie BUFGCTRL_X0Y2.

type t

val create : 
  ?clk_src_bufg:Hardcaml_xilinx_reports__.Import.String.t ->
  name:Hardcaml_xilinx_reports__.Import.String.t ->
  period:Hardcaml_xilinx_reports__.Import.Float.t ->
  Hardcaml_xilinx_reports__.Import.Unit.t ->
  t

Create a clock with the period specified in nanoseconds.

val create_mhz : 
  ?clk_src_bufg:Hardcaml_xilinx_reports__.Import.String.t ->
  name:Hardcaml_xilinx_reports__.Import.String.t ->
  frequency_mhz:Hardcaml_xilinx_reports__.Import.Float.t ->
  Hardcaml_xilinx_reports__.Import.Unit.t ->
  t

Create a clock with the frequency specified in MHz.

val name : t -> Hardcaml_xilinx_reports__.Import.String.t

val period : t -> Hardcaml_xilinx_reports__.Import.Float.t

val clk_src_bufg : 
  t ->
  Hardcaml_xilinx_reports__.Import.String.t
    Hardcaml_xilinx_reports__.Import.Option.t