package hardcaml_xilinx_reports

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package hardcaml_xilinx_reports
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Generate a generic command line for performing synthesis runs over a given design.

module Command_flags : sig ... end
val command_circuit : ?primitive_groups:Primitive_group.t Hardcaml_xilinx_reports__.Import.List.t -> ?sort_by_name:Hardcaml_xilinx_reports__.Import.Bool.t -> (Hardcaml.Scope.t -> Hardcaml.Circuit.t) -> Core.Command.t
val run_circuit : ?primitive_groups:Primitive_group.t Hardcaml_xilinx_reports__.Import.List.t -> ?sort_by_name:Hardcaml_xilinx_reports__.Import.Bool.t -> flags:Command_flags.t -> (Hardcaml.Scope.t -> Hardcaml.Circuit.t) -> Hardcaml_xilinx_reports__.Import.Unit.t Async.Deferred.t
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