package hardcaml

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package hardcaml
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Creation and manipulation of hardware circuits

type t

circuit data structure

val sexp_of_t : t -> Sexplib0.Sexp.t
module Port_checks : sig ... end

Check if the ports specified in the interface match those defined in the circuit.

module Config : sig ... end
val create_exn : ?config:Config.t -> name:Base.string -> Signal.t Base.list -> t

create circuit data structure

val inputs : t -> Signal.t Base.list

return circuit inputs

val outputs : t -> Signal.t Base.list

return circuit outputs

val signal_graph : t -> Signal_graph.t
val name : t -> Base.string

return circuit name

val with_name : t -> name:Base.string -> t

Return identical circuit except for the name.

val is_input : t -> Signal.t -> Base.bool

is the signal an input to the circuit

val is_output : t -> Signal.t -> Base.bool

is the signal an output of the circuit

val find_signal_exn : t -> Hardcaml__.Signal.Uid.t -> Signal.t
val set_phantom_inputs : t -> (Base.string * Base.int) Base.list -> t

For internal use. Add phantom input ports to the circuit when writing RTL. This can be necessary to ensure Interface based input specifications match those discovered when traversing the hardware design from its outputs. It is especially important when working with hierarchical designs.

val phantom_inputs : t -> (Base.string * Base.int) Base.list
module Signal_map : sig ... end

Map of uids to Signal.ts.

val assertions : t -> Signal.t Base.Map.M(Base.String).t
val signal_map : t -> Signal_map.t

Get map of uids to Signal.ts.

val fan_out_map : t -> Hardcaml__.Signal.Type.Uid_set.t Hardcaml__.Signal.Type.Uid_map.t

Compute and return a Fan_out_map.t. The computation is lazy and only performed the first time fan_out_map is called.

val fan_in_map : t -> Hardcaml__.Signal.Type.Uid_set.t Hardcaml__.Signal.Type.Uid_map.t

Compute and return a Fan_in_map.t. The computation is lazy and only performed the first time fan_in_map is called.

val structural_compare : ?check_names:Base.bool -> t -> t -> Base.bool

compare 2 circuits to see if they are the same

val instantiations : t -> Hardcaml__.Signal.Type.instantiation Base.list

returns the list of instantiations in this circuit

val create_with_interface : (module Interface.S_Of_signal with type Of_signal.t = 'i) -> (module Interface.S_Of_signal with type Of_signal.t = 'o) -> ?config:Config.t -> name:Base.string -> ('i -> 'o) -> t
module With_interface (I : Interface.S) (O : Interface.S) : sig ... end
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