package janestreet_cpuid

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Module gateway into Intel specific flags and functionality. *

All of the information in this file comes from (currently) page 792 of the Intel Software Developer's Library (combined 4 volumes), a.k.a the section in Volume 2 detailing the CPUID instruction.

type t
val maximum_leaf : t -> int
val create : Cpuid__.Cpuid_intf.Basic_info.t -> t
module Version_and_feature_information : sig ... end

On Intel CPUs the leaf retrieved when EAX is set to 0x1 contains processor model information as well as some basic features about the processor. Typically if you're checking a flag in this section it's probably available on every machine that we run on (our machines tend towards modernity) but good on you for checking!

val canonical_identifier : t -> string

For identifying which table of perf-events applies for this processor. We use the form specified in the, i.e.: Family-Model-optionalStepping,Version,Filename,EventType GenuineIntel-6-2E,V2,/NHM-EX/NehalemEX_core_V2.json,core GenuineIntel-6-1E,V2,/NHM-EP/NehalemEP_core_V2.json,core GenuineIntel-6-55-01234,V1.12,/SKX/skylakex_core_v1.12.json,core

When family-model pair is not sufficient to identify the supported events, the description includes stepping.

For example, processors in family 6 and model 0x55 from stepping 5 onwards use different perf events than those in previous steppings of the same model.

To distinguish between these two cases, CPU ID format is GenuineIntel-6-55-01234 and GenuineIntel-6-55-56789ABCDEF, instead of GenuineIntel-6-55.

The leaf at 0x7 is special because in addition to putting 0x7 it also lets you put a value into ECX to get a particular feature subleaf. In this case we want ECX=0x0, and any processor which supports EAX=0x7 (which we do check) supports ECX=0x0.


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