package hardcaml-yosys

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in-package search v0.2.0

package hardcaml-yosys

hardcaml-yosys
- HardCamlYosys
  - Cell
  - Import
    
    I
    
    S
  - Io
  - Lvt
    
    Cfg
    
    Make
    
    C
    
    Rd
    
    Wr
    
    Make_wren
    
    C
    
    Rd
    
    Wr
    
    Multiport_regs
    
    C
    
    Rd
    
    Wr
    
    Rd
    
    Wr
  - Techlib
    
    Proof
    
    Cells
    
    I
    
    O
    
    P
    
    W
    
    Make
    
    C
    
    I
    
    O
    
    P
    
    W
    
    Simlib
    
    Adff
    
    I
    
    O
    
    P
    
    W
    
    Concat
    
    I
    
    O
    
    P
    
    W
    
    Dff
    
    I
    
    O
    
    P
    
    W
    
    Dffe
    
    I
    
    O
    
    P
    
    W
    
    Dffsr
    
    I
    
    O
    
    P
    
    W
    
    Fa
    
    I
    
    O
    
    P
    
    W
    
    Lcu
    
    I
    
    O
    
    P
    
    W
    
    Lut
    
    I
    
    O
    
    P
    
    W
    
    Mem
    
    I
    
    O
    
    P
    
    W
    
    Memrd
    
    I
    
    O
    
    P
    
    W
    
    Memwr
    
    I
    
    O
    
    P
    
    W
    
    Mux
    
    I
    
    O
    
    P
    
    W
    
    Op1
    
    I
    
    O
    
    P
    
    W
    
    Op2
    
    I
    
    O
    
    P
    
    W
    
    Pmux
    
    I
    
    O
    
    P
    
    W
    
    Slice
    
    I
    
    O
    
    P
    
    W
    
    Wrapper
    
    I
    
    O
    
    P
  - Yosys_atd_j
  - Yosys_atd_t

Legend:
Library
Module
Module type
Parameter
Class
Class type

type !'a t = {

abits : 'a;
init : 'a;
memid : 'a;
offset : 'a;
size : 'a;
width : 'a;
rd_clk_enable : 'a;
rd_clk_polarity : 'a;
rd_ports : 'a;
rd_transparent : 'a;
wr_clk_enable : 'a;
wr_clk_polarity : 'a;
wr_ports : 'a;

}

val t : (string * int) t

val map : ('a -> 'b) -> 'a t -> 'b t

val map2 : ('a -> 'b -> 'c) -> 'a t -> 'b t -> 'c t

val to_list : 'a t -> 'a list