package hardcaml-yosys

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in-package search v0.2.0

package hardcaml-yosys

hardcaml-yosys
- HardCamlYosys
  - Cell
  - Import
    
    I
    
    S
  - Io
  - Lvt
    
    Cfg
    
    Make
    
    C
    
    Rd
    
    Wr
    
    Make_wren
    
    C
    
    Rd
    
    Wr
    
    Multiport_regs
    
    C
    
    Rd
    
    Wr
    
    Rd
    
    Wr
  - Techlib
    
    Proof
    
    Cells
    
    I
    
    O
    
    P
    
    W
    
    Make
    
    C
    
    I
    
    O
    
    P
    
    W
    
    Simlib
    
    Adff
    
    I
    
    O
    
    P
    
    W
    
    Concat
    
    I
    
    O
    
    P
    
    W
    
    Dff
    
    I
    
    O
    
    P
    
    W
    
    Dffe
    
    I
    
    O
    
    P
    
    W
    
    Dffsr
    
    I
    
    O
    
    P
    
    W
    
    Fa
    
    I
    
    O
    
    P
    
    W
    
    Lcu
    
    I
    
    O
    
    P
    
    W
    
    Lut
    
    I
    
    O
    
    P
    
    W
    
    Mem
    
    I
    
    O
    
    P
    
    W
    
    Memrd
    
    I
    
    O
    
    P
    
    W
    
    Memwr
    
    I
    
    O
    
    P
    
    W
    
    Mux
    
    I
    
    O
    
    P
    
    W
    
    Op1
    
    I
    
    O
    
    P
    
    W
    
    Op2
    
    I
    
    O
    
    P
    
    W
    
    Pmux
    
    I
    
    O
    
    P
    
    W
    
    Slice
    
    I
    
    O
    
    P
    
    W
    
    Wrapper
    
    I
    
    O
    
    P
  - Yosys_atd_j
  - Yosys_atd_t

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Library
Module
Module type
Parameter
Class
Class type

type dyn = Yojson.Safe.json

type direction = [

| `Input
| `Output

]

type bits = dyn list

type port = {

direction : direction;
bits : bits;

}

type param_value = dyn

type attributes = {

src : string;
full_case : int;
parallel_case : int;
init : dyn option;
unused_bits : string option;

}

type netname = {

hide_name : int;
bits : bits;
attributes : attributes;

}

type cell = {

hide_name : int;
typ : string;
parameters : (string * param_value) list;
attributes : attributes;
port_directions : (string * direction) list;
connections : (string * bits) list;

}

type modl = {

ports : (string * port) list;
cells : (string * cell) list;
netnames : (string * netname) list;

}

type t = {

creator : string;
modl : (string * modl) list;

}