hardcaml-yosys

Import Verilog designs into HardCaml
IN THIS PACKAGE
exception Cell_not_in_techlib of string * string
exception Failed_to_find_net of int
exception Input_not_found of string
exception Empty_bus of string
exception Expecting_memory_id
module I : Map.S
module S : Map.S
val load : ?blackbox:bool -> (string list * ( Cell.t -> Techlib.cell ) Techlib.assoc) -> Yosys_atd_t.t -> (int Techlib.assoc * int Techlib.assoc * create_fn) Techlib.assoc