hardcaml-yosys

Import Verilog designs into HardCaml
IN THIS PACKAGE
Parameter #1 HardCamlYosys . Techlib . Proof . Make . C
module W : sig ... end
val cells : W.fn list
val get_input_width : int P.t -> int I.t
val get_output_width : int P.t -> int O.t