hardcaml-yosys

Import Verilog designs into HardCaml
IN THIS PACKAGE
Module HardCamlYosys . Techlib . Simlib . Op2 . O
type !'a t = {
y : 'a;
}
val t : (string * int) t
val map : ( 'a -> 'b ) -> 'a t -> 'b t
val map2 : ( 'a -> 'b -> 'c ) -> 'a t -> 'b t -> 'c t
val to_list : 'a t -> 'a list